CPU |
SH7750F167 (208P QFP) |
Clock |
162 MHz (27 MHz quarts crystal units are used.) |
Operation performance |
300 MIPS / 1.2 GFLOPS |
Memory |
Flash ROM 1 Mbyte (16 bit width)
SDRAM 16 Mbyte (32 bit width)
SRAM 256 Kbyte (16 bit width)
Instruction cache 8 Kbyte
Operating cache 16 Kbyte |
External memory chip
select |
Chip select terminal: 7, PCMCIA interface incorporated
CS0: Flash ROM, CS1: SRAM, CS3: SDRAM used
Each memory is maskable.
CS0 and CS1 are interchangeable. (For debugging.) |
Memory back up |
For switching back-up.
SRAM back up can be achieved by connecting the back-up battery, etc.
to the outside. |
I/O |
Serial interface 2 CH
Parallel interface I/O 20 bit |
Timer/Counter |
32 bit timer 3 channels |
Interruption |
Interruption controller incorporated
External 5 (Level interruption 15) NMI 1, other internal surrounding
interruption |
DMA |
DMA controller incorporated 4 channels |
DRAM |
SDRAM, DRAM controller incorporated |
RTC |
Incorporated clock, calendar function, 32.768 kHz
crystal connected. |
Reset |
Reset switch incorporated. External reset is possible.
(Open collector) |
Operation mode |
Can be switched by DIP-SW. |
External connection |
64 PIN connector x 2 (2.54 pitch)
50 PIN connector x 1 (2.54 pitch)
H-UDI connector 14 pin
Connector for adapter for RS232
Power source connector |
Power source voltage |
5 V ± 10% (Internal I/O: 3.3 V CPU core: 1.8
V) |
Electrical consumption |
MAX 700 mA |
Substrate size |
120 x 90 (mm) 4 layer substrate |
Accessories |
Operation manual, circuit drawing, power cable, sample
program and downloader |